Paper accepted to DAC 2017

February 18th, 2017 No comments

Congratulations!

Our submission to DAC 2017 on stochastic computing based deep neural network, authored by Hyeonuk Sim and others, has been accepted for oral presentation at DAC 2017, Austin, Texas.

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Papers accepted to DATE 2017

November 10th, 2016 No comments

Two papers accepted to DATE 2017. One for oral presentation (first-authored by Atul Rahman), and the other for interactive presentation (first-authored by Dong Nguyen), which does get included in the proceedings though shorter in length. Congratulations!

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Embedded System Design Challenge

October 23rd, 2016 No comments

Embedded System Design Challenge

February, 18, 2017

  • What to do: Optimized design/implementation of “Faster RCNN”
  • How to win: Minimize Energy Concumption
    • Satisfying recognition rate constraint, and
    • Satisfying real-time performance constraint
  • Platform? There are two.
    • Mobile AP (including mobile GPU): Odroid XU4, or
    • BYOB (Bring Your Own Board): anything is okay… (Hardware/software co-design including FPGA, DSP, ASIC, etc.)
    • No network connection allowed
  • Prize: cash prize, internship opportunity, paper recommendation, etc.
  • Interested? Apply here: https://sites.google.com/site/esdc2017/
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Paper accepted to ASP-DAC 2017

October 10th, 2016 No comments

A paper titled “Scalable Stochastic-Computing Accelerator for Convolutional Neural Networks” authored by Hyeonuk Sim and others is accepted to the 22nd Asia and South Pacific Design Automation Conference (ASP-DAC 2017), to be held in Tokyo, Japan in January, 2017. Congratulations!

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Joint-lab Workshop between UNIST & SNU

May 21st, 2016 No comments

snu joint-workshop

We had a joint-lab workshop with SNU last Friday, May 20. The photo is at the Gwanak-mountain hiking right after the workshop.

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Congrats! Samsung Human Tech Paper Award

February 15th, 2016 No comments

Congratulations!

Atul Rahman and other members (Hyeon Uk Sim and Dong Nguyen) of the Renew Lab have won the highly competitive Samsung Human Tech Paper Award. The paper is titled “Efficient FPGA Acceleration of Convolutional DNNs Using 3D Compute Array”, and the only entry from UNIST in the category of CSE (Computer Science and Engineering). The award is extremely selective, and the acceptance rate was only about 6% this year.

This is the first time this award was given to School of ECE, UNIST, though there are three other teams from the school who won the award, all in different categories.

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Paper accepted to DATE 2016

November 12th, 2015 No comments

The ECL lab at UNIST has one paper accepted to the 2016 Design, Automation and Test in Europe (DATE) conference, to be held in Dresden, Germany, March 14 ~ 18, 2016. Following is the information of the accepted paper:

  • Title: Efficient FPGA Acceleration of Convolutional DNNs Using Logical 3D Compute Array
  • Authors: Atul Rahman, Jongeun Lee and Kiyoung Choi

Congratulations!

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Paper accepted to CGO 2016

November 11th, 2015 No comments

The ECL lab has one paper accepted to the 2016 International Symposium on Code Generation and Optimization (CGO), to be held in Barcelona, Spain, March 12 ~ 18, 2016. The following is the information of the accepted paper:

  • Title: Communication-aware Multi-GPU Mapping for Stream Graphs
  • Authors: Dong Nguyen and Jongeun Lee

Congratulations!

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ECL members

June 4th, 2015 No comments

ECL members in front of Engineering Building 2.

ECL Members in front of Engineering Building 2, on a beautiful day in May.

Tip: You can watch more pictures like this in Categories | Album.

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Internship position available

June 4th, 2015 No comments

Internship Positions at ECL, UNIST

The Embedded Computing Laboratory at UNIST is recruiting 
multiple undergraduate researchers in the broad area of 
brain-inspired computing as described below.

 

FPGA-based Deep Learning

Recent advances in deep learning are in large part due to the increased computing capability of off-the-shelf processors. To enable further advances in this direction, this project explores the use of “programmable hardware”, or FPGA (Field-Programmable Gate Array) technology, for the acceleration of deep neural networks such as convolutional neural networks. In a broader context, this research topic is about the application of hardware-software co-design principles to machine learning algorithms, which has many implications and is in active research nowadays.

This topic is best suited for students majoring in both CSE and EE (it doesn’t matter whichever is the 1st major). Prerequisites include Computer Organization, and exposure to hardware description languages is a strong plus. Knowledge of Machine Learning or Artificial Intelligence is a plus, but not required.

Stochastic Deep Neural Network

Creating a Deep Neural Network (DNN) processor has many appeals. A DNN processor can be much more efficient than CPU/GPU/FPGA-based implementations, thus enabling a host of interesting applications (e.g., real-time image recognition), and being a processor, it can be applied to many different neural network applications. Challenges however include how to make it scalable to large and small networks. One idea is to apply Stochastic Computing (SC). SC is a new way of representing numbers and performing arithmetic operations, and radically different from conventional digital computing and enables much more compact implementations of complex functions.

Best candidates for this topic should have strong math skills (especially in probability). Machine learning or hardware design is not a requirement.

 

Interested students should contact Prof. Lee.

Note: These research positions are related to Samsung Future Technology Project.

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