Archive

Author Archive

Sugil Lee

March 2nd, 2017 No comments

Sugil Lee

Sugil Lee joined the lab in March, 2017 as a master student. He majored in mathematics with some background in CS. His research interests include machine learning.

Categories: People Tags:

Paper accepted to DAC 2017

February 18th, 2017 No comments

Congratulations!

Our submission to DAC 2017 on stochastic computing based deep neural network, authored by Hyeonuk Sim and others, has been accepted for oral presentation at DAC 2017, Austin, Texas.

Categories: News Tags:

Papers accepted to DATE 2017

November 10th, 2016 No comments

Two papers accepted to DATE 2017. One for oral presentation (first-authored by Atul Rahman), and the other for interactive presentation (first-authored by Dong Nguyen), which does get included in the proceedings though shorter in length. Congratulations!

Categories: News Tags:

Embedded System Design Challenge

October 23rd, 2016 No comments

Embedded System Design Challenge

February, 18, 2017

  • What to do: Optimized design/implementation of “Faster RCNN”
  • How to win: Minimize Energy Concumption
    • Satisfying recognition rate constraint, and
    • Satisfying real-time performance constraint
  • Platform? There are two.
    • Mobile AP (including mobile GPU): Odroid XU4, or
    • BYOB (Bring Your Own Board): anything is okay… (Hardware/software co-design including FPGA, DSP, ASIC, etc.)
    • No network connection allowed
  • Prize: cash prize, internship opportunity, paper recommendation, etc.
  • Interested? Apply here: https://sites.google.com/site/esdc2017/
Categories: News Tags:

Paper accepted to ASP-DAC 2017

October 10th, 2016 No comments

A paper titled “Scalable Stochastic-Computing Accelerator for Convolutional Neural Networks” authored by Hyeonuk Sim and others is accepted to the 22nd Asia and South Pacific Design Automation Conference (ASP-DAC 2017), to be held in Tokyo, Japan in January, 2017. Congratulations!

Categories: News Tags:

Aidyn Zhakatayev

September 20th, 2016 No comments

Aidyn Zhakatayev

Aidyn Zhakatayev started his M.S. program in September, 2016. He majored in EE with a double major in CSE from UNIST, which should give him a perfect background for his research into various aspects of stochastic computing and deep neural networks. He enjoys football, and is from Kazakstan.

He is the first author of a paper presented at Design Automation Conference, June 2018. After graduation he joined Deeplite, an AI-driven deep neural network optimizer company, in Montréal, Canada.

Categories: People Tags:

Daewoo Kim

September 3rd, 2016 No comments

Daewoo Kim

Daewoo Kim joined the lab in August, 2016 for his M.S. program staring in Fall, 2016. He has a CS background but is also very competent in various areas of hardware design including processor design, accelerator design for emerging application such as deep learning, and high level synthesis.

After graduation he joined LG Electronics, in the Home Appliance Division, in Guro-gu, Seoul, Korea.

Categories: People Tags:

Joint-lab Workshop between UNIST & SNU

May 21st, 2016 No comments

snu joint-workshop

We had a joint-lab workshop with SNU last Friday, May 20. The photo is at the Gwanak-mountain hiking right after the workshop.

Categories: Album, News Tags:

Congrats! Samsung Human Tech Paper Award

February 15th, 2016 No comments

Congratulations!

Atul Rahman and other members (Hyeon Uk Sim and Dong Nguyen) of the Renew Lab have won the highly competitive Samsung Human Tech Paper Award. The paper is titled “Efficient FPGA Acceleration of Convolutional DNNs Using 3D Compute Array”, and the only entry from UNIST in the category of CSE (Computer Science and Engineering). The award is extremely selective, and the acceptance rate was only about 6% this year.

This is the first time this award was given to School of ECE, UNIST, though there are three other teams from the school who won the award, all in different categories.

Categories: News Tags:

Paper accepted to DATE 2016

November 12th, 2015 No comments

The ICCL lab at UNIST has one paper accepted to the 2016 Design, Automation and Test in Europe (DATE) conference, to be held in Dresden, Germany, March 14 ~ 18, 2016. Following is the information of the accepted paper:

  • Title: Efficient FPGA Acceleration of Convolutional DNNs Using Logical 3D Compute Array
  • Authors: Atul Rahman, Jongeun Lee and Kiyoung Choi

Congratulations!

Categories: News Tags: