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Two interactive presentation papers in DATE 2013

March 25th, 2013 No comments

In this year’s DATE (Design, Automation & Test in Europe), which is the largest European conference in the EDA (Electronic Design Automation) field, we have contributed two interactive presentation (IP) papers, which are published in 4 pages each and will appear in the IEEE Xplore as well. Congrats to those participants!

Here is the paper information (follow the links for full text).

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Runtime and Install-time Binary Translation for Reconfigurable Accelerators

January 28th, 2013 No comments

In his masters thesis defense on Jan 9th, 2013, Toan presented an approach called Runtime Binary Translation (RBT) that can dynamically make use of the CGRA accelerator existing in a CGRA-based reconfigurable computing system to speedup the execution of application intermediate representation (IR) on top of a just-in-time (JIT) compiler. ย A simpler approach called Install-time Binary Translation (IBT) based on RBT is also proposed. Here is the abstract of the thesis. ๐Ÿ˜€

Nowadays, softwares are often distributed in form of some machine-independent intermediate representation (IR), because compared to machine-dependent native binary, the IR is more portable across a wide range of architectures, has better security, and contains richer semantic information. However, the problem of making use of the accelerator in a target machine to speedup the execution of the IR on top of a just-in-time compiler (JIT) is challenging, mainly because the discovery of compute-intensive kernels and the partitioning of the application to the kernel and sequential parts must be done based on the IR alone, without the access to the program source code as well as the kernel information in the IR.

In this work, we propose a Runtime Binary Translation (RBT) technique that can dynamically identify and translate kernels IR to Coarse-Grained Reconfigurable Array (CGRA) accelerator configuration, and offload the execution of the kernels onto the accelerator. Also, we simplify the RBT approach to make the Install-time Binary Translation (IBT) approach, which does the partitioning and the translation right at the install-time instead of at the runtime. Experimental results show that our RBT and IBT techniques can improve the runtime of the application IR by 1.44 times and 1.61 times, respectively, compare to the runtime on the JIT that does not support making use of the accelerator.

 

Runtime Binary Translation Virtual Machine Optimized Design

Toan Passes Thesis Defense

January 10th, 2013 No comments

Congratulations, Toan!

Yesterday, January 9, Toan successfully defended his thesis on Runtime and Install-time Binary Translation for Reconfigurable Accelerators.ย Though there are some minor things he has to finish before he can get the approval signatures from the committee members, the thesis committee was in general agreement that he did a good job for a masters degree, based on his achievements during the graduate program and his thesis writing.

Now that he is seeking an industry career at the moment, the ECL lab wishes him a good luck in his career and a good fortune too! ๐Ÿ™‚

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CSE211 Intro to PL – Textbook Change

November 2nd, 2012 No comments

Important Notice

To students taking CSE211: Introduction to Programming Languages, in the 3rd term of 2012.

The required textbook for this course is changed to Concepts of Programming Languages by Robert W. Sebesta, 10th edition, Addison-Wesley. You can purchase the textbook at the campus bookstore or online.

Jongeun Lee, The Instructor

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Seminar Schedule

September 16th, 2012 No comments

Seminar Schedule for September/October (Place is EB1 E204 unless noted otherwise.)

Cloud Random Access Network (C-RAN)

  • Speaker:ย Dr. Saewoong Bahk, Seoul National University
  • Date:ย September 19
  • Title:ย Evolution of Wi-Fi on Cloud-RAN: Complementary Utilization of Unlicensed Spectrum

Flash Memory Technology

  • Speaker: Dr. Taehoon Kim, Intel-Micron joint R&D team for memory devices
  • Date: September 26
  • Title: Challenges & Future Directions for Flash & Emerging Nonvolatile memories for 2D & 3D realization

Automotive

  • Speaker: Dr. Seungyoung Ahn, KAIST
  • Date: October 10
  • Title: Future Green Transportation with Wireless Power Transfer Technology

Mobile Application Processor

  • Speaker: Dr. Jeong-Ho Woo, Texas Instruments
  • Date: October 23
  • Title: Design Paradigm of Mobile Application Processor

Multiprocessor Architecture: Design and Implementation

  • Speaker: Dr. Jongmyon Kim, University of Ulsan
  • Date: October 24
  • Title: Mobile Multimedia Supercomputer Design
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Paper accepted to FPT as oral presentation

August 8th, 2012 No comments

Our paper titled “Software-Managed Automatic Data Sharing forย Coarse-Grained Reconfigurable Coprocessors” is accepted as an oral presentation in theย International Conference on Field Programming Technology (FPT) 2012, which will be held in Seoul, Dec 10~12.

Congratulations to those who participated in this work!

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Wanted: Undergraduate Students interested in AI (Artificial Intelligence) or HW design

August 8th, 2012 No comments

omok
Yes, you read it correctly. ย It’s a rare combination of AI (Artificial Intelligence) and HW (Hardware) design skills, that is in want.

There is a national and an international competition that is scheduled around October, on FPGA designs that can play the “Connect-6” game. The connect-6 game is a variation of “Five-in-a-Row” (or Omok as is called in Korea), and the trick is that you have to make a hardware in FPGA that can play the game in real-time. The timing constraint is 1 min, and you have to come up with the best solution within the min — otherwise you’ll forfeit your chance to make a move.

*Highlights of this competition

  • First place winner of the national level will be given a MKE-ministry award (์ง€๊ฒฝ๋ถ€ ์žฅ๊ด€์ƒ), which is very prestigious.
  • National level winners will enter the international level.
  • International level winners will be recognized with cash prizes during an international conference (FPT), and their design summary will be published in the conference proceedings.

More details can be found in the conference website.

Sounds interesting? ย Contact the lab.ย Don’t worry if you don’t have any knowledge/experience with AI or HW design — not expected (but you should be at least a junior majoring in ECE).

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Front page changed

August 3rd, 2012 No comments

Some dynamic elements are added to the front page, which now shows a slideshow instead of a random picture. The slideshow controls are also provided (previous, next, and pause/resume). The previous and next buttons are easy to spot, but where is the pause/resume button?

The answer is the page number.

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Connect-6 Design Contest

March 7th, 2012 No comments

As part of the 2012 International Conference on Field Programming Technology, there will be a design contest for the best/fastest Connect-6 game designs.

For more details see website: http://www.eecg.toronto.edu/~janders/FPT_2011_competition/ (it is for the previous year, but this year’s rules will be similar)

๋˜ ํ•œ ๊ฐ€์ง€ ์ค‘์š”ํ•œ ์ •๋ณด๋Š” ์ด ๊ตญ์ œ ๋Œ€ํšŒ๋ฅผ ์ค€๋น„ํ•˜๊ธฐ ์œ„ํ•˜์—ฌ ๊ตญ๋‚ด ๋Œ€ํšŒ๋ฅผ ๊ฐœ์ตœํ•  ์˜ˆ์ •์ž…๋‹ˆ๋‹ค. ๊ตญ๋‚ด์—์„œ ์ฒ˜์Œ์œผ๋กœ ๊ฐœ์ตœ๋˜๋Š” ๋Œ€ํšŒ์ด๊ณ  ์•„์ง ๊ณต์‹ ๋ฐœํ‘œ๋œ ๊ฒƒ์ด ์•„๋‹ˆ๊ธฐ ๋•Œ๋ฌธ์— ๋ˆ„๊ตฌ๋“ ์ง€ ์ง€๊ธˆ๋ถ€ํ„ฐ๋ผ๋„ ์ค€๋น„ํ•˜๋ฉด ๊ดœ์ฐฎ์€ ๊ฒฐ๊ณผ๋ฅผ ์–ป์„ ์ˆ˜ ์žˆ์Šต๋‹ˆ๋‹ค. ๋˜ ์ฒ˜์Œ ๊ฐœ์ตœ๋˜๋Š” ๋Œ€ํšŒ๋ผ์„œ ์ฐธ๊ฐ€์ž๋ฅผ ์œ ์ธํ•˜๊ธฐ ์œ„ํ•˜์—ฌ ๋งŽ์€ ์ƒ์ด ๋งˆ๋ จ๋˜์–ด ์žˆ๋Š” ๊ฒƒ์œผ๋กœ ์•Œ๊ณ  ์žˆ์Šต๋‹ˆ๋‹ค. ๊ด€์‹ฌ ์žˆ๋Š” ํ•™์ƒ์€ ๋ฌธ์˜๋ฐ”๋ž๋‹ˆ๋‹ค.

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ACM TACO (HiPEAC 2012) paper accepted!

November 23rd, 2011 No comments

This time, HiPEAC tries a new publication model. Instead of first publishing your paper in a conference, they do a journal review process for all submitted papers, and those accepted papers will have a chance to get presented in a conference, in addition to the journal publication. Our paper on nested loop compilation for reconfigurable architectures, was accepted for this journal issue. Congrats to those involved in this work!

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