Optimized ASIP Synthesis from Architecture Description Language Models
, Heinrich Meyr
and Rainer Leupers
--공부를 목적으로 위 책을 참고하여 내용을 정리함--
Four major reasons for ASIC desgin challange
- Deep-submicron effects are not considered on the abstraction level used for architectural specipication.
- Larger chips can be implemented due to the advances in semiconductor manufacturing.
- Not only the amount of gates, but also the complexity of the designs is increasing.
- The shrinking time-to-market as well as the shortened time-in-market augment the challenges in ASIP design.
-Due to the above-mentioned reasons, SoC
building blocks need to be designed for reuse and adaption.
- ASICs provide only a fixed fuction and not the required flexibility. However, ASICs are required in SoC designs due to their high performance as well as energy efficiency.
- ASIC can be divided into two components
- Data-path : computaional units, storage elements and multiplexers to route the data.
- control-path : Finite State Machine(FSM) that controls the datapath.
- The FSM represents the applicaion dependent schedule of operations. Due to its complexity and irregularity, design errors are more likely to appear in the control-path than in the data-path of the architecture. Although the separation between data-path and control-path is theoretically existent, unfortunately, traditional ASIC design combines these components without a clear interface.
- This certainly affects the initial specification, but even more the reuse and adaption of the ASIC. Every variation of the ASIC has to be completely verified even if only the control-path is changed.
- Application-Specific Instruction-Set Processors
- Hot spots of the application must be accelerated by an applicaion-specific and optimized data-path while its control must be flexible and easy to verify.
- Seperation between fixed data-path and flexible control. Here, errors which ensue from the complex applicaion dependent control can be easily eliminated by software updates.
- Due to their generality, GPPs, DSPs or uCs and neither achieve the performance nor the energy efficiency of ASICs.
- ASIPs which incorporate the flexibility of processors and high performance and energy efficiency of ASICs.
- Heterogeneous Architectures: Computational Performance vs. Flexibility
- Heterogeneous architectures combine existing architecture types to satisfy the demands of Soc design
- Architectures currently discussed in academia and industry are presented in the following
- MultiProcessor(MP) solutions
- A Processor with a loosely/tightly coupled accelerator
- A Processor with loosly/tightly coupled FPGA
- FPGAs with integrated processors
- The heterogeneous solutions mentioned above compete with ASIPs with regard to flexibility, performance, power dissipaion and design efficiency. The particular characteristics of ASIPs are explained in the following.
- Applicaion_Spesific Instruction-Set Processors
- Challenges of ASIP Design