A Coarse-Grained Array Accelerator for Software-Defined Radio Baseband Processing


  • What?
    • Coarse-grained array accelerators for high performance, low power Software-Defined Radio.
  • why?
    • Energy budget for mobile devices are shrinking
    • Communication Standards are getting more complex
    • Traditional implementations
      • Integrate multiple radios & baseband ICs
      • Cost-ineffective.
    • Software-Defined Radios (SDRs):
      • deploy baseband processing on programmable/reconfigurable processors.
      • more flexible & cost-effective.
    • Technology scaling cannot sustain the complexity & throughput increase
    • -> revise architectures to achieve & still maintain energy budgets acceptable for hand-held integration (300mW)
      • Characteristics of wireless baseband processing:
        • inner loops (called kernel) take most of the computation time.
        • feature high data-level parallelism (DLP) & high instruction-level parallelism (ILP)
  • Some details:
    • Architecture:
      • A main CPU
      • C-programmable CGA-SIMD SDR accelerator
        • exploits high ILP available in SDR kernels
        • combine with simple & effective DLP support
    • Unified compiler
      • maps sequential nonkernel ANSI C code on to the main CPU
      • maps *loops" from that same code onto the accelerator.
Topic revision: r4 - 27 Mar 2011, ToanMai
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