A Coarse-Grained Array Accelerator for Software-Defined Radio Baseband Processing
Coarse-grained array accelerators for high performance, low power Software-Defined Radio.
Energy budget for mobile devices are shrinking
Communication Standards are getting more complex
Integrate multiple radios & baseband ICs
Software-Defined Radios (SDRs):
deploy baseband processing on programmable/reconfigurable processors.
more flexible & cost-effective.
Technology scaling cannot sustain the
complexity & throughput
-> revise architectures to achieve & still maintain
acceptable for hand-held integration
Characteristics of wireless baseband processing:
inner loops (called kernel)
take most of the computation time.
high data-level parallelism (DLP) & high instruction-level parallelism (ILP)
A main CPU
C-programmable CGA-SIMD SDR accelerator
exploits high ILP available in SDR kernels
combine with simple & effective DLP support
ANSI C code on to the main CPU
maps *loops" from that same code onto the accelerator.
This topic: Main
27 Mar 2011,
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