Department of electrical engineering, KAIST, Daejeon, Korea
Former manager at Intel
PhD in EE, Stanford University; MS & BS in EE, SNU.
Abstract: For the past four decades, relentless focus on transistor scaling and Moore’s Law led to ever-higher transistor performance and density, resulting in tremendous increases in functionality and performance. Historically, transistor scaling meant so-called "classic scaling" which was proposed by Dennard where gate oxide thickness (Tox), transistor length (Lg) and transistor width (W) were scaled by a constant factor (1/k) in order to provide a delay improvement of 1/k at constant power density. As the transistor gate length and the gate oxide thickness scale down, physical limitations, such as off-state leakage current and power density, make geometric scaling an increasingly challenging task. The introduction of strain silicon technology using embedded SiGe source/drain and high stress capping layers and high-k + metal gate transistors broke through some of these scaling barriers, continuing Moore’s Law. However, as dimensions are further reduced beyond 32nm node, there are a number of challenges to be overcome: capacitance, resistance, gate control, channel mobility, and variation. To continue historical trends of both area and performance improvement, novel solutions are required. This talk will review historical transistor scaling trends, traditional device scaling issues andrecent developments in the strain silicon and high-k + metal gate technology, including both gate-first and gate-last approaches, and then discuss potential future directions for continuing Moore’s Law into the next decade.