Publications

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Journal Articles


  1. Double MAC on a DSP: Boosting the Performance of Convolutional Neural Networks on FPGAs, Sugil Lee, Daewoo Kim, Dong Nguyen, and Jongeun Lee**, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2018.

  2. An Efficient and Accurate Stochastic Number Generator Using Even-distribution Coding, Aidyn Zhakatayev, Kyounghoon Kim, Jongeun Lee**, and Kiyoung Choi, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2018.

  3. Efficient Execution of Stream Graphs on Coarse-Grained Reconfigurable Architectures, Sangyun Oh, Hongsik Lee, and Jongeun Lee**, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 36(12), pp. 1978-1988, December, 2017.

  4. Efficient High-Level Synthesis for Nested Loops of Nonrectangular Iteration Spaces, Hyeonuk Sim, Atul Rahman, and Jongeun Lee**, IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, 24(8), pp. 2799-2802, August, 2016.

  5. Mapping Imperfect Loops to Coarse-Grained Reconfigurable Architectures, Hyeonuk Sim, Hongsik Lee, Seongseok Seo, and Jongeun Lee**, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 35(7), pp. 1092-1104, IEEE Press, July, 2016.

  6. Scalable Application Mapping for SIMD Reconfigurable Architecture, Yongjoo Kim, Jinyong Lee, Jongeun Lee*, and Yunheung Paek, Journal of Semiconductor Technology and Science, 6(15), pp. 634-646, IEEK, December, 2015.

  7. Improving Performance of Loops on DIAM-based VLIW Architectures, Jinyong Lee, Jongwon Lee, Jongeun Lee, and Yunheung Paek, ACM SIGPLAN Notices (LCTES '14), 49(5), pp. 135-144, ACM, June, 2014.

  8. Configurable Range Memory for Effective Data Reuse on Programmable Accelerators, Jongeun Lee**, Seongseok Seo, Jongkyung Paek, and Kiyoung Choi, ACM Transactions on Design Automation of Electronic Systems (TODAES), 19(2), pp. 13:1-13:22, ACM, March, 2014.

  9. Design and Optimization for Embedded and Real-time Computing Systems and Applications, Jongeun Lee*, Steve Goddard, and Chin-Fu Kuo, Journal of Systems Architecture, 60(2), pp. 151, February, 2014. (Editorial of a special issue for RTCSA '12)

  10. Evaluator-executor Transformation for Efficient Pipelining of Loops with Conditionals, Yeonghun Jeong, Seongseok Seo, and Jongeun Lee**, ACM Transactions on Architecture and Code Optimization (TACO), 10(4), pp. 62:1-62:23, ACM, December, 2013.

  11. Software-based Register File Vulnerability Reduction for Embedded Processors, Jongeun Lee and Aviral Shrivastava, ACM Transactions on Embedded Computing Systems (TECS), 13(1s), pp. 38:1-38:20, ACM, November, 2013.

  12. Architecture Customization of On-Chip Reconfigurable Accelerators, Jonghee W. Yoon, Jongeun Lee*, Sanghyun Park, Yongjoo Kim, Jinyong Lee, Yunheung Paek, and Doosan Cho, ACM Transactions on Design Automation of Electronic Systems (TODAES), 18(4), pp. 52:1-52:22, ACM, October, 2013.

  13. PICA: Processor Idle Cycle Aggregation for Energy-Efficient Embedded Systems, Jongeun Lee and Aviral Shrivastava, ACM Transactions on Embedded Computing Systems (TECS), 11(2), pp. 26:1-26:27, ACM, July, 2012.

  14. Return Data Interleaving for Multi-Channel Embedded CMPs Systems, Fei Hong, Aviral Shrivastava, and Jongeun Lee, IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, 20(7), pp. 1351-1354, IEEE, July, 2012.

  15. Improving Performance of Nested Loops on Reconfigurable Array Processors, Yongjoo Kim, Jongeun Lee*, Toan X. Mai, and Yunheung Paek, ACM Transactions on Architecture and Code Optimization (TACO), 8(4), pp. 32:1-32:23, ACM, January, 2012.

  16. High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures, Yongjoo Kim, Jongeun Lee*, Aviral Shrivastava, Jonghee W. Yoon, Doosan Cho, and Yunheung Paek, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 30(11), pp. 1599-1609, IEEE, November, 2011.

  17. Memory Access Optimization in Compilation for Coarse Grained Reconfigurable Architectures, Yongjoo Kim, Jongeun Lee*, Aviral Shrivastava, and Yunheung Paek, ACM Transactions on Design Automation of Electronic Systems (TODAES), 16(4), pp. 42:1-42:27, ACM, October, 2011.

  18. Fast graph-based instruction selection for multi-output instructions, Jonghee M. Youn, Jongwon Lee, Yunheung Paek, Jongeun Lee*, Hanno Scharwaechter, and Rainer Leupers, Software: Practice & Experience (SP&E), 41(6), pp. 717-736, Wiley, May, 2011.

  19. Static Analysis of Register File Vulnerability, Jongeun Lee and Aviral Shrivastava, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 30(4), pp. 607-616, IEEE, April, 2011.

  20. Binary Acceleration Using Coarse-Grained Reconfigurable Architecture, Jong Kyung Paek, Kiyoung Choi, and Jongeun Lee, SIGARCH Computer Architecture News, 38(4), pp. 33-39, ACM, September, 2010.

  21. A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files, Jongeun Lee and Aviral Shrivastava, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 29(7), pp. 1018-1027, IEEE Press, July, 2010.

  22. Operation and Data Mapping for CGRAs with Multi-Bank Memory, Yongjoo Kim, Jongeun Lee*, Aviral Shrivastava, and Yunheung Paek, ACM SIGPLAN Notices (LCTES '10), 45(4), pp. 17-26, April, 2010. (18 papers accepted out of 58 submissions, 31.0% acceptance rate)

  23. Cache Vulnerability Equations for Protecting Data in Embedded Processor Caches from Soft Errors, Aviral Shrivastava, Jongeun Lee*, and Reiley Jeyapaul, ACM SIGPLAN Notices (LCTES '10), 45(4), pp. 143-152, April, 2010. (Second Highest Ranked Paper)

  24. A Software-Only Solution to Use Scratch Pads for Stack Data, Aviral Shrivastava, Arun Kannan, and Jongeun Lee*, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 28(11), pp. 1719-1727, November, 2009.

  25. A Compiler Optimization to Reduce Soft Errors in Register Files, Jongeun Lee and Aviral Shrivastava, ACM SIGPLAN Notices (LCTES '09), 44(7), pp. 41-49, ACM, July, 2009. (18 papers accepted out of 81 submissions, 22.2% acceptance rate)


Conference Papers


  1. Efficient FPGA Implementation of Local Binary Convolutional Neural Network, Aidyn Zhakatayev and Jongeun Lee**, Proc. of the 24th Asia and South Pacific Design Automation Conference (ASP-DAC), January, 2019.

  2. On-chip Memory Optimization for High-level Synthesis of Multi-dimensional Data on FPGA, Daewoo Kim, Sugil Lee, and Jongeun Lee**, Proc. of the 24th Asia and South Pacific Design Automation Conference (ASP-DAC), January, 2019.

  3. Log-Quantized Stochastic Computing for Memory and Computation Efficient DNNs, Hyeonuk Sim and Jongeun Lee**, Proc. of the 24th Asia and South Pacific Design Automation Conference (ASP-DAC), January, 2019.

  4. XOMA: Exclusive On-Chip Memory Architecture for Energy-Efficient Deep Learning Acceleration, Hyeonuk Sim, Jason H. Anderson, and Jongeun Lee**, Proc. of the 24th Asia and South Pacific Design Automation Conference (ASP-DAC), January, 2019.

  5. FPGA Architecture Enhancements for Efficient BNN Implementation, Jin-Hee Kim, Jongeun Lee, and Jason H. Anderson, Proc. of IEEE International Conference on Field Programmable Technology (FPT), December, 2018.

  6. Overcoming Crossbar Nonidealities in Binary Neural Networks Through Learning, Mohammed E. Fouda, Jongeun Lee, Ahmed M. Eltawil, and Fadi Kurdahi, Proc. of 14th IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), July, 2018.

  7. DPS: Dynamic Precision Scaling for Stochastic Computing-Based Deep Neural Networks, Hyeonuk Sim, Saken Kenzhegulov, and Jongeun Lee**, Proc. of 55th Annual ACM/IEEE Design Automation Conference (DAC), June, 2018.

  8. Sign-Magnitude SC: Getting 10X Accuracy for Free in Stochastic Computing for Deep Neural Networks, Aidyn Zhakatayev, Sugil Lee, Hyeonuk Sim, and Jongeun Lee**, Proc. of 55th Annual ACM/IEEE Design Automation Conference (DAC), June, 2018.

  9. Architecture Exploration of Standard-Cell and FPGA-Overlay CGRAs Using the Open-Source CGRA-ME Framework, S. Alexander Chin, Kuang Ping Niu, Matthew Walker, Shizhang Yin, Alexander Mertens, Jongeun Lee, and Jason H. Anderson, Proc. of International Symposium on Physical Design (ISPD), March, 2018.

  10. FPGA Implementation of Convolutional Neural Network Based on Stochastic Computing, Daewoo Kim, Mansureh S. Moghaddam, Hossein Moradian, Hyeonuk Sim, Jongeun Lee**, and Kiyoung Choi, Proc. of IEEE International Conference on Field-Programmable Technology (FPT), pp. 287-290, December, 2017.

  11. Accurate and Efficient Stochastic Computing Hardware for Convolutional Neural Networks, Joonsang Yu, Kyounghoon Kim, Jongeun Lee*, and Kiyoung Choi, Proc. of IEEE International Conference on Computer Design (ICCD), pp. 105-112, November, 2017.

  12. A New Stochastic Computing Multiplier with Application to Deep Convolutional Neural Networks, Hyeonuk Sim and Jongeun Lee**, Proc. of 54th Annual ACM/IEEE Design Automation Conference (DAC), pp. 29:1-29:6, June, 2017.

  13. Design Space Exploration of FPGA Accelerators for Convolutional Neural Networks, Atul Rahman, Sangyun Oh, Jongeun Lee**, and Kiyoung Choi, Proc. of Design, Automation and Test in Europe (DATE), pp. 1147-1152, March, 2017.

  14. Double MAC: Doubling the Performance of Convolutional Neural Networks on Modern FPGAs, Dong Nguyen, Daewoo Kim, and Jongeun Lee**, Proc. of Design, Automation and Test in Europe (DATE), pp. 890-893, March, 2017.

  15. Scalable Stochastic-Computing Accelerator for Convolutional Neural Networks, Hyeonuk Sim, Dong Nguyen, Jongeun Lee**, and Kiyoung Choi, Proc. of the 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 696-701, January, 2017.

  16. A New Approach to Binarizing Neural Networks, Jungwoo Seo, Joonsang Yu, Jongeun Lee, and Kiyoung Choi, Proc. of the 13th International SoC Design Conference (ISOCC), pp. 77-78, October, 2016.

  17. Dynamic Energy-Accuracy Trade-off Using Stochastic Computing in Deep Neural Networks, Kyounghoon Kim, Jungki Kim, Joonsang Yu, Jungwoo Seo, Jongeun Lee, and Kiyoung Choi, Proc. of 53rd Annual ACM/IEEE Design Automation Conference (DAC), June, 2016.

  18. Efficient FPGA Acceleration of Convolutional Neural Networks Using Logical-3D Compute Array, Atul Rahman, Jongeun Lee**, and Kiyoung Choi, Proc. of Design, Automation and Test in Europe (DATE), March, 2016.

  19. Communication-Aware Mapping of Stream Graphs for Multi-GPU Platforms, Dong Nguyen and Jongeun Lee**, Proc. of the 2016 International Symposium on Code Generation and Optimization (CGO), ACM, March, 2016.

  20. An Energy-Efficient Random Number Generator for Stochastic Circuits, Kyounghoon Kim, Jongeun Lee, and Kiyoung Choi, Proc. of the 21st Asia and South Pacific Design Automation Conference (ASP-DAC), January, 2016.

  21. Approximate De-randomizer for Stochastic Circuits, Kyounghoon Kim, Jongeun Lee, and Kiyoung Choi, Proc. of the 12th International SoC Design Conference (ISOCC), November, 2015.

  22. Optimizing Stream Program Performance on CGRA-based Systems, Hongsik Lee, Dong Nguyen, and Jongeun Lee**, Proc. of the 52nd Annual Design Automation Conference (DAC), pp. 110:1-110:6, ACM, 2015.

  23. Flattening-based Mapping of Imperfect Loop Nests for CGRAs, Jongeun Lee**, Seongseok Seo, Hongsik Lee, and Hyeon Uk Sim, Proc. of the 2014 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 9:1-9:10, ACM, 2014. (30 papers accepted out of 117 submissions, 25% acceptance rate)

  24. Efficient Software-Based Runtime Binary Translation for Coarse-Grained Reconfigurable Architectures, Toan X. Mai and Jongeun Lee**, Proc. of the 2014 IEEE International Parallel & Distributed Processing Symposium (IPDPS) Workshops (RAW), pp. 132-140, IEEE Computer Society, May, 2014.

  25. Compiling Control-Intensive Loops for CGRAs with State-Based Full Predication, Kyuseung Han, Kiyoung Choi, and Jongeun Lee, Proc. of Design, Automation and Test in Europe (DATE), pp. 1579-1582, March, 2013.

  26. Fast Shared On-Chip Memory Architecture for Efficient Hybrid Computing with CGRAs, Jongeun Lee**, Yeonghun Jeong, and Sungsok Seo, Proc. of Design, Automation and Test in Europe (DATE), pp. 1575-1578, March, 2013.

  27. Software-Managed Automatic Data Sharing for Coarse-Grained Reconfigurable Coprocessors, Toan X. Mai and Jongeun Lee**, Proc. of IEEE International Conference on Field-Programmable Technology (FPT), pp. 277-284, December, 2012.

  28. Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable Architecture, Yongjoo Kim, Jongeun Lee*, Jinyong Lee, Toan X. Mai, Ingoo Heo, and Yunheung Paek, Proc. of International Symposium on Applied Reconfigurable Computing (ARC), Lecture Notes in Computer Science, vol. 7199, pp. 40-52, March, 2012.

  29. CRM: Configurable Range Memory for Fast Reconfigurable Computing, Jongkyung Paek, Jongeun Lee*, and Kiyoung Choi, Proc. of Reconfigurable Architecture Workshop (RAW), pp. 158-165, May, 2011.

  30. I2CRF: Incremental Interconnect Customization for Embedded Reconfigurable Fabrics, Jonghee W. Yoon, Jongeun Lee*, Jaewan Jung, Sanghyun Park, Yongjoo Kim, Yunheung Paek, and Doosan Cho, Proc. of Design, Automation and Test in Europe (DATE), pp. 206-211, March, 2011.

  31. Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays, Yongjoo Kim, Jongeun Lee*, Aviral Shrivastava, Jonghee W. Yoon, and Yunheung Paek, Proc. of International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), Lecture Notes in Computer Science, vol. 5952, pp. 171-185, January, 2010.

  32. Static Analysis to Mitigate Soft Errors in Register Files, Jongeun Lee and Aviral Shrivastava, Proc. of Design, Automation and Test in Europe (DATE), April, 2009.

  33. FSAF: File System Aware Flash Translation Layer for NAND Flash Memories, Sai Mylavarapu, S. Choudhuri, Aviral Shrivastava, and Jongeun Lee, Proc. of Design, Automation and Test in Europe (DATE), April, 2009.

  34. Compiler-Managed Register File Protection for Energy-Efficient Soft Error Reduction, Jongeun Lee and Aviral Shrivastava, Proc. of the 14th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 618-623, January, 2009.

  35. A Software Solution for Dynamic Stack Management on Scratch Pad Memory, Arun Kannan, Aviral Shrivastava, Amit Pabalkar, and Jongeun Lee, Proc. of the 14th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 612-617, January, 2009.


Domestic Conference Papers


  1. Reducing FPGA Area Using Nano-Switch Devices in Inter and Intra-Logic Routing, Aidyn Zhakatayev and Jongeun Lee**, Proc. of the 25th Korean Conference on Semiconductors, February, 2018.

  2. Pipelining Nested Loops with Triangular Iteration Space for High-Level Synthesis, Atul Rahman, Hyeonuk Sim, and Jongeun Lee**, Proc. of the 22nd Korean Conference on Semiconductors, February, 2015.

  3. Optimization of Streaming Application with Limited Scratch-pad Memory on Coarse-Grained Reconfigurable Architecture, Hongsik Lee and Jongeun Lee, Proc. of the 22nd Korean Conference on Semiconductors, February, 2015.

  4. Optimal Resource-aware Mapping of Stream Graphs to GP-GPUs, Dong Nguyen and Jongeun Lee, Proc. of the 22nd Korean Conference on Semiconductors, February, 2015.

  5. New Processing Element for Imperfect Nested Loops on Coarse Grained Reconfigurable Architecture, Seongseok Seo, Hyeonuk Sim, and Jongeun Lee, Proc. of the 21st Korean Conference on Semiconductors, February, 2014.

  6. FPGA Prototyping of Programmable Regular Iterator Generator, Hyeonuk Sim, Seongseok Seo, and Jongeun Lee, Proc. of the 21st Korean Conference on Semiconductors, February, 2014.

  7. Mapping DSP Loops to Reconfigurable Processor Accelerators, Sungsok Seo, Yeonghun Jeong, and Jongeun Lee, Proc. of the 20th Korean Conference on Semiconductors, February, 2013.

  8. Selective Execution of Conditional Statements for CGRAs, Yeonghun Jeong, Sungsok Seo, and Jongeun Lee, Proc. of the 20th Korean Conference on Semiconductors, February, 2013. (Best Paper Award)

  9. Promoting Data Reuse on Shared Memory of Hybrid System, Toan X. Mai, Yeonghun Jeong, and Jongeun Lee, Proc. of the 19th Korean Conference on Semiconductors, pp. 593-594, February, 2012.


Master's Theses


  1. Dong Nguyen, Communication-aware Mapping of Stream Graphs for Multi-GPU Platforms, Ulsan National Institute of Science and Technology, February, 2016.
    Thesis Committee: Jongeun Lee (Chair), Woongki Baek, and Wonki Jeong.

  2. Hongsik Lee, Application-Level Performance Improvement for Stream Program on CGRA-based systems, Ulsan National Institute of Science and Technology, February, 2016.
    Thesis Committee: Jongeun Lee (Chair), Woongki Baek, and Seokhyeong Kang.

  3. Seongseok Seo, Scaling Kernel Speedup to Application-level Performance with CGRAs: Stream Program Approach, Ulsan National Institute of Science and Technology, February, 2014.
    Thesis Committee: Jongeun Lee (Chair), Won-ki Jeong, and Giljin Jang.

  4. Yeonghun Jeong, Evaluator-executor Transformation for Efficient Conditional Statements on CGRA, Ulsan National Institute of Science and Technology, June, 2013.
    Thesis Committee: Jongeun Lee (Chair), Won-ki Jeong, and Youngri Choi.

  5. Toan X. Mai, Runtime and Install-time Binary Translation for Reconfigurable Accelerators, Ulsan National Institute of Science and Technology, February, 2013.
    Thesis Committee: Jongeun Lee (Chair), Beomseok Nam, and Won-Ki Jeong.