June 22nd, 2017

At Reconfigurable and Neuromorphic Computing Lab (RNCL) in UNIST, we are mainly concerned with the problems of optmizing system performance and power at the intersection of software and hardware. At the core of information technology is computation, which is realized through the combination of hardware and software. But today both hardware and software are seeing fundamental changes, forecasting a paradigm shift in how we understand and realize computation. This shift is caused first by the changes and advances in hardware technology, in particular, semiconductor device technology, forcing us to seek new boundaries between hardware and software, such as application-specific processors, hardware accelerators, and even reconfigurable processors. The second cause of the shift is the emergence and pervasive use of deep learning systems. Deep learning hardware is not programmed in the conventional way such as sequential or parallel programming, but what is called “training”, or iterative application of relevant data through the learning pathway of the system. Thus deep learning systems provide a real possibility of new computer architectures that are not based on von Neumann abstraction but more like the human brain. At RNCL, as we are doing research involving both hardware and software components of a system, we are in a unique position of being able to perform original research that can pave the way for the paradigm shift in the core definition of computing.

우리 연구실은 기본적으로 소프트웨어와 하드웨어의 경계에서 시스템 성능이나 전력 등을 최적화할 수 있는 다양한 기법들을 연구하고 있습니다. 특히나 오늘날의 컴퓨터는 두가지 중요한 패러다임의 변화를 준비하고 있습니다. 하나는 꾸준히 하드웨어 기술이 발전함에 따라, 하드웨어와 소프트웨어의 경계를 허물거나 기존의 폰노이만 컴퓨터 패러다임을 변경하는 연구 수요와 관심이 매우 높아지고 있다는 것이고, 다른 측면에서는, 최근에 등장한 딥러닝을 중심으로 기존의 순차적 또는 병렬 프로그래밍 방식이 아닌 데이터가 곧 프로그램이 되는 새로운 프로그래밍 패러다임을 제시하는 차세대 컴퓨팅 시스템에 대한 연구가 요구된다는 것입니다. 소프트웨어와 하드웨어 분야의 중심에 있음으로써 우리 연구실은, 컴퓨터가 직면한 두가지 패러다임의 변화를 리드하는 경쟁력있는 연구가 가능합니다.

Research Areas

  • Deep learning and neuromorphic processor
  • New and emerging device based electronic design paradigm (e.g. stochastic computing, NVM)
  • Compilation for emerging architectures (e.g. multicore processor, GPUs, FPGA, reconfigurable processor)
  • Electronic design automation (EDA)


Recent Projects

Check out the front page, featuring interesting research outcomes from our lab.

1. Heterogeneous Parallel Computing

February 10th, 2014editor

Heterogeneous Parallel Computing (HPC) is about utilizing a set of very different processors such as CPU and GPU efficiently and with ease. The HPC Research Group in ECL lab is actively addressing the following research questions to help realize better heterogeneous parallel computing platforms and applications.

Research Agenda

  • communication problem
    • between CPU and accelerators (GPU, VLIW, loop accelerators, ASIC, etc.)
  • memory organization and management problem
    • shared memory? cache? scratch-pad memory?
  • domain specific architecture
    • for example, computer vision or machine learning


  • Fast Shared On-Chip Memory Architecture for Efficient Hybrid Computing with CGRAs, Jongeun Lee, Yeonghun Jeong, and Sungsok Seo, Proc. of Design, Automation and Test in Europe (DATE ’13), March, 2013.
  • Software-Managed Automatic Data Sharing for Coarse-Grained Reconfigurable Coprocessors, Toan X. Mai and Jongeun Lee*, Proc. of International Conference on Field-Programmable Technology (FPT ’12), pp. 277-284, December, 2012.
  • CRM: Configurable Range Memory for Fast Reconfigurable Computing, Jongkyung Paek, Jongeun Lee*, and Kiyoung Choi, Proc. of Reconfigurable Architecture Workshop (RAW ’11), pp. 158-165, May, 2011.

Related Articles

2. Reconfigurable Computing

December 9th, 2013editor

Multi-core and even many-core processors have been successfully used in other domains. Reconfigurable array processors, for instance, have been actively researched and used as an on-chip accelerator for stream processing applications and embedded processors, due to their extremely low power and high performance execution, compared to general purpose processors or even DSPs (digital signal processors).

However, the main challenge in such accelerator-type reconfigurable processors is compilation — the problem of how to map applications onto the architecture. At the heart of this problem is the 2D placement-and-routing problem, which is traditionally recognized as a CAD problem, which is why this problem is often discussed in the design automation communities. Still the problem needs more research and development efforts (such as mature tool chains) for more wide-spread adoption of the architecture.

The ECL Lab is actively pursuing research on this topic, with a few specific goals in mind. We have two granted projects on this, partially in collaboration with other labs.


Figure 1: An accelerator-type reconfigurable processor architecture (Bougard et al. ’08).

Research Questions

  • how to compile the usual C programs (“legacy”) onto coarse-grained reconfigurable architectures?
  • can there be good architectural solutions (such as architecture extensions) to make it much easier to map programs to these architectures (“compiler-friendly architectures”)?
  • what are the real bottleneck to enhancing performance through these processors and how to address them?
    • application level mapping problem


  • Compiling Control-Intensive Loops for CGRAs with State-Based Full Predication, Kyuseung Han, Kiyoung Choi, and Jongeun Lee, Proc. of Design, Automation and Test in Europe (DATE ’13), March, 2013.
  • Architecture Customization of On-Chip Reconfigurable Accelerators, Jonghee W. Yoon, Jongeun Lee*, Sanghyun Park, Yongjoo Kim, Jinyong Lee, Yunheung Paek, and Doosan Cho, ACM Transactions on Design Automation of Electronic Systems (TODAES), 18(4), pp. 52:1-52:22, ACM, October, 2013.
  • Improving Performance of Nested Loops on Reconfigurable Array Processors, Yongjoo Kim, Jongeun Lee*, Toan X. Mai, and Yunheung Paek, ACM Transactions on Architecture and Code Optimization (TACO), 8(4), pp. 32:1-32:23, ACM, January, 2012.
  • Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable Architecture, Yongjoo Kim, Jongeun Lee*, Jinyong Lee, Toan X. Mai, Ingoo Heo, and Yunheung Paek, Proc. of International Symposium on Applied Reconfigurable Computing (ARC ’12), Lecture Notes in Computer Science, vol. 7199, pp. 40-52, March, 2012.
  • High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures, Yongjoo Kim, Jongeun Lee*, Aviral Shrivastava, Jonghee W. Yoon, Doosan Cho, and Yunheung Paek, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 30(11), pp. 1599-1609, IEEE, November, 2011.
  • Memory Access Optimization in Compilation for Coarse Grained Reconfigurable Architectures, Yongjoo Kim, Jongeun Lee*, Aviral Shrivastava, and Yunheung Paek, ACM Transactions on Design Automation of Electronic Systems (TODAES), 16(4), pp. 42:1-42:27, ACM, October, 2011.

Related Articles

3. Multi-core Computing

February 7th, 2011editor

Parallel processing, or multi-core compilation, is rather a challenge than a blessing, since it means the era of free ride is over. When the hardware performance kept doubling every 18 months, the same software could be run twice as before by running it on a new hardware. But now it is no longer true, unless the software can somehow exploit the increased parallelism by the new machine.

There are many challenges including how to compile applications, or in particular, how to map code and data onto various heterogeneous as well as homogeneous processor cores, and manage them efficiently. The management must include aspects of not only performance optimization, but of thermal management, energy and power optimization (such as Dynamic Voltage and Frequency Scaling), and reliability (such as soft error resilience). These multi-dimensional, multi-objective problems require innovative ideas and approaches on architecture, compiler, computer-aided design, operating system, and algorithm levels.

In ECL Lab, we are particularly looking at data management problems for distributed memory architectures such as the Cell processor architecture, where simple scratchpad memories are used instead of power-hungry caches to save power.


Figure 1: Sony/Toshiba/IBM Cell.


  • Software-based Register File Vulnerability Reduction for Embedded Processors, Jongeun Lee and Aviral Shrivastava, ACM Transactions on Embedded Computing Systems (TECS), 13(1s), pp. 38:1-38:20, ACM, November, 2013.
  • Return Data Interleaving for Multi-Channel Embedded CMPs Systems, Fei Hong, Aviral Shrivastava, and Jongeun Lee, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 20(7), pp. 1351-1354, IEEE, July, 2012.
  • Static Analysis of Register File Vulnerability, Jongeun Lee and Aviral Shrivastava, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 30(4), pp. 607-616, IEEE, April, 2011.
  • A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files, Jongeun Lee and Aviral Shrivastava, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 29(7), pp. 1018-1027, IEEE Press, July, 2010.
  • Cache Vulnerability Equations for Protecting Data in Embedded Processor Caches from Soft Errors, Aviral Shrivastava, Jongeun Lee*, and Reiley Jeyapaul, ACM SIGPLAN Notices (LCTES ’10), 45(4), pp. 143-152, April, 2010.
  • A Software-Only Solution to Use Scratch Pads for Stack Data, Aviral Shrivastava, Arun Kannan, and Jongeun Lee*, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 28(11), pp. 1719-1727, November, 2009.

See Research Archive for more.