Jongeun Lee
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Selected Publications

Note: ACM Publication Free Download List

View [Chronological] [Pre-1900] [BibTeX]
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Book Chapters


'Synthesis of Instruction Sets for High-Performance and Energy-Efficient ASIP'
Jongeun Lee, Kiyoung Choi and Nikil Dutt
Designing Embedded Processors: A Low Power Perspective,
Jorg Henkel and Sri Parameswaran, eds., Springer 2007.
ISBN: 978-1-4020-5868-4

International Conference Papers


  1. Hyperdimensional Computing as a Rescue for Efficient Privacy-Preserving Machine Learning-as-a-Service, Jaewoo Park, Chenghao Quan, Hyungon Moon* and Jongeun Lee**, Proc. of International Conference on Computer-Aided Design (ICCAD), October, 2023.
  2. Accelerating Transformers with Fourier-Based Attention for Efficient On-Device Inference, Hyeonjin Jo, Chaerin Sim, Jaewoo Park and Jongeun Lee**, Proc. of the 20th International SoC Design Conference (ISOCC), October, 2023.
  3. NTT-PIM: Row-Centric Architecture and Mapping for Efficient Number-Theoretic Transform on PIM, Jaewoo Park, Sugil Lee and Jongeun Lee**, Proc. of the 60th Annual ACM/IEEE Design Automation Conference (DAC), pp. 1-6, July, 2023.
  4. Centered Symmetric Quantization for Hardware-Efficient Low-Bit Neural Networks, Faaiz Asim, Jaewoo Park, Azat Azamat and Jongeun Lee**, Proc. of British Machine Vision Conference (BMVC), November, 2022.
  5. Squeezing Accumulators in Binary Neural Networks for Extremely Resource-Constrained Applications, Azat Azamat, Jaewoo Park and Jongeun Lee**, Proc. of International Conference on Computer-Aided Design (ICCAD), October, 2022.
  6. Multi-Fidelity Nonideality Simulation and Evaluation Framework for Resistive Neuromorphic Computing, Chenghao Quan, Mohammed E. Fouda, Sugil Lee and Jongeun Lee**, Proc. of 2022 56th Asilomar Conference on Signals, Systems, and Computers, pp. 1152-1156, October, 2022.
  7. Accurate Prediction of ReRAM Crossbar Performance Under I-V Nonlinearity and IR Drop, Sugil Lee, Mohammed Fouda, Jongeun Lee**, Ahmed Eltawil and Fadi Kurdahi, Proc. of International Conference on Computer Design (ICCD), pp. 9-16, October, 2022.
  8. Non-Uniform Step Size Quantization for Accurate Post-Training Quantization, Sangyun Oh, Hyeonuk Sim, Jounghyun Kim and Jongeun Lee**, Proc. of European Conference on Computer Vision (ECCV), October, 2022.
  9. Quarry: Quantization-based ADC Reduction for ReRAM-based Deep Neural Network Accelerators, Azat Azamat, Faaiz Asim and Jongeun Lee**, Proc. of International Conference on Computer-Aided Design (ICCAD), pp. 1-7, November, 2021.
  10. Fast and Low-Cost Mitigation of ReRAM Variability for Deep Learning Applications, Sugil Lee, Mohammed Fouda, Jongeun Lee**, Ahmed Eltawil and Fadi Kurdahi, Proc. of International Conference on Computer Design (ICCD), pp. 269-276, October, 2021.
  11. Automated Log-Scale Quantization for Low-Cost Deep Neural Networks, Sangyun Oh, Hyeonuk Sim, Sugil Lee and Jongeun Lee**, Proc. of Conference on Computer Vision and Pattern Recognition (CVPR), pp. 742-751, June, 2021.
  12. Cost- and Dataset-free Stuck-at Fault Mitigation for ReRAM-based Deep Learning Accelerators, Giju Jung, Mohammed Fouda, Sugil Lee, Jongeun Lee**, Ahmed Eltawil and Fadi Kurdahi, Proc. of Design, Automation and Test in Europe (DATE), pp. 1733-1738, February, 2021.
  13. NP-CGRA: Extending CGRAs for Efficient Processing of Light-weight Deep Neural Networks, Jungi Lee and Jongeun Lee**, Proc. of Design, Automation and Test in Europe (DATE), pp. 1408-1413, February, 2021.
  14. Architecture-Accuracy Co-optimization of ReRAM-based Low-cost Neural Network Processor, Segi Lee, Sugil Lee, Jongeun Lee**, Jong-Moon Choi, Do-Wan Kwon, Seung-Kwang Hong and Kee-Won Kwon, Proc. of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 427-432, September, 2020.
  15. SparTANN: Sparse Training Accelerator for Neural Networks with Threshold-based Sparsification, Hyeonuk Sim, Jooyeon Choi and Jongeun Lee**, Proc. of ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 211-216, August, 2020.
  16. Learning to Predict IR Drop with Effective Training for ReRAM-based Neural Network Hardware, Sugil Lee, Mohammed Fouda, Jongeun Lee**, Ahmed Eltawil and Fadi Kurdahi, Proc. of the 57th Annual ACM/IEEE Design Automation Conference (DAC), pp. 1-6, July, 2020.
  17. Successive Log Quantization for Cost-Efficient Neural Networks Using Stochastic Computing, Sugil Lee, Hyeonuk Sim, Jooyeon Choi and Jongeun Lee**, Proc. of the 56th Annual ACM/IEEE Design Automation Conference (DAC), pp. 7:1-7:6, June, 2019.
  18. Efficient FPGA Implementation of Local Binary Convolutional Neural Network, Aidyn Zhakatayev and Jongeun Lee**, Proc. of the 24th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 699-704, January, 2019.
  19. On-chip Memory Optimization for High-level Synthesis of Multi-dimensional Data on FPGA, Daewoo Kim, Sugil Lee and Jongeun Lee**, Proc. of the 24th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 243-248, January, 2019.
  20. Log-Quantized Stochastic Computing for Memory and Computation Efficient DNNs, Hyeonuk Sim and Jongeun Lee**, Proc. of the 24th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 280-285, January, 2019.
  21. XOMA: Exclusive On-Chip Memory Architecture for Energy-Efficient Deep Learning Acceleration, Hyeonuk Sim, Jason H. Anderson and Jongeun Lee**, Proc. of the 24th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 651-656, January, 2019.
  22. FPGA Architecture Enhancements for Efficient BNN Implementation, Jin-Hee Kim, Jongeun Lee and Jason H. Anderson, Proc. of IEEE International Conference on Field Programmable Technology (FPT), pp. 214-221, December, 2018.
  23. Overcoming Crossbar Nonidealities in Binary Neural Networks Through Learning, Mohammed E. Fouda, Jongeun Lee, Ahmed M. Eltawil and Fadi Kurdahi, Proc. of the 14th IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), July, 2018.
  24. Fast and Light-Weight Unsupervised Depth Estimation for Mobile GPU Hardware, Sangyun Oh, Jongeun Lee and Hye-Jin S. Kim, Proc. of Computer Vision and Pattern Recognition Workshops (CVPRW), Deep Vision, July, 2018.
  25. DPS: Dynamic Precision Scaling for Stochastic Computing-Based Deep Neural Networks, Hyeonuk Sim, Saken Kenzhegulov and Jongeun Lee**, Proc. of the 55th Annual ACM/IEEE Design Automation Conference (DAC), pp. 13:1-13:6, June, 2018.
  26. Sign-Magnitude SC: Getting 10X Accuracy for Free in Stochastic Computing for Deep Neural Networks, Aidyn Zhakatayev, Sugil Lee, Hyeonuk Sim and Jongeun Lee**, Proc. of the 55th Annual ACM/IEEE Design Automation Conference (DAC), pp. 158:1-158:6, June, 2018.
  27. Architecture Exploration of Standard-Cell and FPGA-Overlay CGRAs Using the Open-Source CGRA-ME Framework, S. Alexander Chin, Kuang Ping Niu, Matthew Walker, Shizhang Yin, Alexander Mertens, Jongeun Lee and Jason H. Anderson, Proc. of International Symposium on Physical Design (ISPD), March, 2018.
  28. FPGA Implementation of Convolutional Neural Network Based on Stochastic Computing, Daewoo Kim, Mansureh S. Moghaddam, Hossein Moradian, Hyeonuk Sim, Jongeun Lee** and Kiyoung Choi, Proc. of IEEE International Conference on Field-Programmable Technology (FPT), pp. 287-290, December, 2017.
  29. Accurate and Efficient Stochastic Computing Hardware for Convolutional Neural Networks, Joonsang Yu, Kyounghoon Kim, Jongeun Lee* and Kiyoung Choi, Proc. of IEEE International Conference on Computer Design (ICCD), pp. 105-112, November, 2017.
  30. A New Stochastic Computing Multiplier with Application to Deep Convolutional Neural Networks, Hyeonuk Sim and Jongeun Lee**, Proc. of the 54th Annual ACM/IEEE Design Automation Conference (DAC), pp. 29:1-29:6, June, 2017.
  31. Design Space Exploration of FPGA Accelerators for Convolutional Neural Networks, Atul Rahman, Sangyun Oh, Jongeun Lee** and Kiyoung Choi, Proc. of Design, Automation and Test in Europe (DATE), pp. 1147-1152, March, 2017.
  32. Double MAC: Doubling the Performance of Convolutional Neural Networks on Modern FPGAs, Dong Nguyen, Daewoo Kim and Jongeun Lee**, Proc. of Design, Automation and Test in Europe (DATE), pp. 890-893, March, 2017.
  33. Scalable Stochastic-Computing Accelerator for Convolutional Neural Networks, Hyeonuk Sim, Dong Nguyen, Jongeun Lee** and Kiyoung Choi, Proc. of the 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 696-701, January, 2017.
  34. A New Approach to Binarizing Neural Networks, Jungwoo Seo, Joonsang Yu, Jongeun Lee and Kiyoung Choi, Proc. of the 13th International SoC Design Conference (ISOCC), pp. 77-78, October, 2016.
  35. Dynamic Energy-Accuracy Trade-off Using Stochastic Computing in Deep Neural Networks, Kyounghoon Kim, Jungki Kim, Joonsang Yu, Jungwoo Seo, Jongeun Lee and Kiyoung Choi, Proc. of the 53rd Annual ACM/IEEE Design Automation Conference (DAC), pp. 124:1-124:6, June, 2016.
  36. Efficient FPGA Acceleration of Convolutional Neural Networks Using Logical-3D Compute Array, Atul Rahman, Jongeun Lee** and Kiyoung Choi, Proc. of Design, Automation and Test in Europe (DATE), pp. 1393-1398, March, 2016.
  37. Communication-Aware Mapping of Stream Graphs for Multi-GPU Platforms, Dong Nguyen and Jongeun Lee**, Proc. of the 2016 International Symposium on Code Generation and Optimization (CGO), pp. 94-104, ACM, March, 2016.
  38. An Energy-Efficient Random Number Generator for Stochastic Circuits, Kyounghoon Kim, Jongeun Lee and Kiyoung Choi, Proc. of the 21st Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 256-261, January, 2016.
  39. Approximate De-randomizer for Stochastic Circuits, Kyounghoon Kim, Jongeun Lee and Kiyoung Choi, Proc. of the 12th International SoC Design Conference (ISOCC), November, 2015.
  40. Optimizing Stream Program Performance on CGRA-based Systems, Hongsik Lee, Dong Nguyen and Jongeun Lee**, Proc. of the 52nd Annual Design Automation Conference (DAC), pp. 110:1-110:6, ACM, June, 2015.
  41. Flattening-based Mapping of Imperfect Loop Nests for CGRAs, Jongeun Lee**, Seongseok Seo, Hongsik Lee and Hyeon Uk Sim, Proc. of the 2014 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 9:1-9:10, ACM, October, 2014. (30 papers accepted out of 117 submissions, 25% acceptance rate)
  42. Efficient Software-Based Runtime Binary Translation for Coarse-Grained Reconfigurable Architectures, Toan X. Mai and Jongeun Lee**, Proc. of the 2014 IEEE International Parallel & Distributed Processing Symposium (IPDPS) Workshops (RAW), pp. 132-140, IEEE Computer Society, May, 2014.
  43. Compiling Control-Intensive Loops for CGRAs with State-Based Full Predication, Kyuseung Han, Kiyoung Choi and Jongeun Lee, Proc. of Design, Automation and Test in Europe (DATE), pp. 1579-1582, March, 2013.
  44. Fast Shared On-Chip Memory Architecture for Efficient Hybrid Computing with CGRAs, Jongeun Lee**, Yeonghun Jeong and Sungsok Seo, Proc. of Design, Automation and Test in Europe (DATE), pp. 1575-1578, March, 2013.
  45. Software-Managed Automatic Data Sharing for Coarse-Grained Reconfigurable Coprocessors, Toan X. Mai and Jongeun Lee**, Proc. of IEEE International Conference on Field-Programmable Technology (FPT), pp. 277-284, December, 2012.
  46. Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable Architecture, Yongjoo Kim, Jongeun Lee*, Jinyong Lee, Toan X. Mai, Ingoo Heo and Yunheung Paek, Proc. of International Symposium on Applied Reconfigurable Computing (ARC), Lecture Notes in Computer Science, vol. 7199, pp. 40-52, March, 2012.
  47. Techniques for improving coarse-grained reconfigurable architectures, Kyuseung Han, Seongsik Park, Kiyoung Choi, Jong Kyung Paek and Jongeun Lee, Proc. of 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1-4, August, 2011.
  48. CRM: Configurable Range Memory for Fast Reconfigurable Computing, Jongkyung Paek, Jongeun Lee* and Kiyoung Choi, Proc. of Reconfigurable Architecture Workshop (RAW), pp. 158-165, May, 2011.
  49. I2CRF: Incremental Interconnect Customization for Embedded Reconfigurable Fabrics, Jonghee W. Yoon, Jongeun Lee*, Jaewan Jung, Sanghyun Park, Yongjoo Kim, Yunheung Paek and Doosan Cho, Proc. of Design, Automation and Test in Europe (DATE), pp. 206-211, March, 2011.
  50. Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays, Yongjoo Kim, Jongeun Lee*, Aviral Shrivastava, Jonghee W. Yoon and Yunheung Paek, Proc. of International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), Lecture Notes in Computer Science, vol. 5952, pp. 171-185, January, 2010.
  51. Static Analysis to Mitigate Soft Errors in Register Files, Jongeun Lee and Aviral Shrivastava, Proc. of Design, Automation and Test in Europe (DATE), April, 2009.
  52. FSAF: File System Aware Flash Translation Layer for NAND Flash Memories, Sai Mylavarapu, S. Choudhuri, Aviral Shrivastava and Jongeun Lee, Proc. of Design, Automation and Test in Europe (DATE), April, 2009.
  53. Compiler-Managed Register File Protection for Energy-Efficient Soft Error Reduction, Jongeun Lee and Aviral Shrivastava, Proc. of the 14th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 618-623, January, 2009.
  54. A Software Solution for Dynamic Stack Management on Scratch Pad Memory, Arun Kannan, Aviral Shrivastava, Amit Pabalkar and Jongeun Lee, Proc. of the 14th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 612-617, January, 2009.
  55. Static Analysis of Processor Stall Cycle Aggregation, Jongeun Lee and Aviral Shrivastava, Proc. of IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 25-30, ACM, October, 2008.
  56. SDRM: Simultaneous Determination of Regions and Function-to-Region Mapping for Scratchpad Memories, Amit Pabalkar, Aviral Shrivastava, Arun Kannan and Jongeun Lee, Proc. of International Conference on on High Performance Computing (HiPC), December, 2008.
  57. Reconfigurable ALU Array Architecture with Conditional Execution, Jongeun Lee, Yoonjin Kim, Jinyong Jung, Shinwon Kang and Kiyoung Choi, Proc. of International SoC Design Conference, pp. 222-226, , 2004.
  58. Energy-Efficient Instruction Set Synthesis for Application-Specific Processors, Jongeun Lee, Kiyoung Choi and Nikil Dutt, Proc. of ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 330-333, , 2003.
  59. Evaluating Memory Architectures for Media Applications on Coarse-Grained Reconfigurable Architectures, Jongeun Lee, Kiyoung Choi and Nikil Dutt, Proc. of IEEE Conference on Application-Specific Systems, Architectures, and Processors (ASAP), pp. 172-182, June, 2003.
  60. Efficient Instruction Encoding for Automatic Instruction Set Design of Configurable ASIPs, Jongeun Lee, Kiyoung Choi and Nikil Dutt, Proc. of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 649-654, , 2002.
  61. Fast Hardware-Software Coverification by Optimistic Execution of Real Processor, Sungjoo Yoo, Jongeun Lee, Jinyong Jung, Kyeongseok Rha, Youngchul Cho and Kiyoung Choi, Proc. of Design, Automation and Test in Europe (DATE), , 2000.
  62. Fast Prototyping of an IS-95 CDMA Cellular Phone: A Case Study, Sungjoo Yoo, Jongeun Lee, Jinyong Jung, Kyeongseok Rha, Youngchul Cho and Kiyoung Choi, Proc. of Asia Pacific Conference on Hardware Description Languages (APCHDL), , 1999.

International Journal Articles


  1. Partial Sum Quantization for Reducing ADC Size in ReRAM-based Neural Network Accelerators, Azat Azamat, Faaiz Asim, Jintae Kim and Jongeun Lee**, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), , 2023.
  2. Kernel Code Integrity Protection at the Physical Address Level on RISC-V, Seon Ha, Minsang Yu, Hyungon Moon and Jongeun Lee, IEEE Access, 11, pp. 62358-62367, June, 2023.
  3. Training-Free Stuck-at Fault Mitigation for ReRAM-based Deep Learning Accelerators, Chenghao Quan, Mohammed E. Fouda, Sugil Lee, Giju Jung, Jongeun Lee**, Ahmed Eltawil and Fadi Kurdahi, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 42(7), pp. 2174-2186, July, 2023. (Date of Publication: 15 November 2022)
  4. Offline Training-based Mitigation of IR Drop for ReRAM-based Deep Neural Network Accelerators, Sugil Lee, Mohammed E. Fouda, Jongeun Lee**, Ahmed Eltawil and Fadi Kurdahi, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 42(2), pp. 521-532, February, 2023. (Date of Publication: 23 May 2022)
  5. MLogNet: A Logarithmic Quantization-Based Accelerator for Depthwise Separable Convolution, Jooyeon Choi, Hyeonuk Sim, Sangyun Oh, Sugil Lee and Jongeun Lee**, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 41(12), pp. 5220-5231, December, 2022. (Date of Publication: 09 February 2022)
  6. Specializing CGRAs for Light-Weight Convolutional Neural Networks, Jungi Lee and Jongeun Lee**, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 41(10), pp. 3387-3399, October, 2022. (Date of Publication: 26 October 2021)
  7. IR-QNN Framework: An IR Drop-Aware Offline Training of Quantized Crossbar Arrays, Mohammed E. Fouda, Sugil Lee, Jongeun Lee, Gun Hwan Kim, Fadi Kurdahi and Ahmed Eltawil, IEEE Access, 8, pp. 228392-228408, IEEE, December, 2020.
  8. Bitstream-based Neural Network for Scalable, Efficient and Accurate Deep Learning Hardware, Hyeonuk Sim and Jongeun Lee**, Frontiers in Neuroscience, 14, pp. 1198, Frontiers, December, 2020.
  9. RRNet: Repetition-Reduction Network for Energy Efficient Depth Estimation, Sangyun Oh, Hye-Jin S. Kim, Jongeun Lee and Junmo Kim, IEEE Access, 8, pp. 106097-106108, IEEE, June, 2020.
  10. Cost-effective Stochastic MAC Circuits for Deep Neural Networks, Hyeonuk Sim and Jongeun Lee**, Neural Networks, 117, pp. 152-162, Elsevier, September, 2019.
  11. Mask Technique for Fast and Efficient Training of Binary Resistive Crossbar Arrays, Mohammed E. Fouda, Sugil Lee, Jongeun Lee, Ahmed Eltawil and Fadi Kurdahi, IEEE Transactions on Nanotechnology, 18, pp. 704-716, IEEE, July, 2019.
  12. Double MAC on a DSP: Boosting the Performance of Convolutional Neural Networks on FPGAs, Sugil Lee, Daewoo Kim, Dong Nguyen and Jongeun Lee**, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 38(5), pp. 888-897, May, 2019.
  13. An Efficient and Accurate Stochastic Number Generator Using Even-distribution Coding, Aidyn Zhakatayev, Kyounghoon Kim, Jongeun Lee** and Kiyoung Choi, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 37(12), pp. 3056-3066, December, 2018.
  14. Efficient Execution of Stream Graphs on Coarse-Grained Reconfigurable Architectures, Sangyun Oh, Hongsik Lee and Jongeun Lee**, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 36(12), pp. 1978-1988, December, 2017.
  15. Efficient High-Level Synthesis for Nested Loops of Nonrectangular Iteration Spaces, Hyeonuk Sim, Atul Rahman and Jongeun Lee**, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 24(8), pp. 2799-2802, August, 2016.
  16. Mapping Imperfect Loops to Coarse-Grained Reconfigurable Architectures, Hyeonuk Sim, Hongsik Lee, Seongseok Seo and Jongeun Lee**, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 35(7), pp. 1092-1104, IEEE Press, July, 2016.
  17. Scalable Application Mapping for SIMD Reconfigurable Architecture, Yongjoo Kim, Jinyong Lee, Jongeun Lee* and Yunheung Paek, Journal of Semiconductor Technology and Science, 6(15), pp. 634-646, IEEK, December, 2015.
  18. Improving Performance of Loops on DIAM-based VLIW Architectures, Jinyong Lee, Jongwon Lee, Jongeun Lee and Yunheung Paek, ACM SIGPLAN Notices (LCTES '14), 49(5), pp. 135-144, ACM, June, 2014.
  19. Configurable Range Memory for Effective Data Reuse on Programmable Accelerators, Jongeun Lee**, Seongseok Seo, Jongkyung Paek and Kiyoung Choi, ACM Transactions on Design Automation of Electronic Systems (TODAES), 19(2), pp. 13:1-13:22, ACM, March, 2014.
  20. Design and Optimization for Embedded and Real-time Computing Systems and Applications, Jongeun Lee*, Steve Goddard and Chin-Fu Kuo, Journal of Systems Architecture, 60(2), pp. 151, February, 2014. (Editorial of a special issue for RTCSA '12)
  21. Evaluator-executor Transformation for Efficient Pipelining of Loops with Conditionals, Yeonghun Jeong, Seongseok Seo and Jongeun Lee**, ACM Transactions on Architecture and Code Optimization (TACO), 10(4), pp. 62:1-62:23, ACM, December, 2013.
  22. Software-based Register File Vulnerability Reduction for Embedded Processors, Jongeun Lee and Aviral Shrivastava, ACM Transactions on Embedded Computing Systems (TECS), 13(1s), pp. 38:1-38:20, ACM, November, 2013.
  23. Architecture Customization of On-Chip Reconfigurable Accelerators, Jonghee W. Yoon, Jongeun Lee*, Sanghyun Park, Yongjoo Kim, Jinyong Lee, Yunheung Paek and Doosan Cho, ACM Transactions on Design Automation of Electronic Systems (TODAES), 18(4), pp. 52:1-52:22, ACM, October, 2013.
  24. PICA: Processor Idle Cycle Aggregation for Energy-Efficient Embedded Systems, Jongeun Lee and Aviral Shrivastava, ACM Transactions on Embedded Computing Systems (TECS), 11(2), pp. 26:1-26:27, ACM, July, 2012.
  25. Return Data Interleaving for Multi-Channel Embedded CMPs Systems, Fei Hong, Aviral Shrivastava and Jongeun Lee, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 20(7), pp. 1351-1354, IEEE, July, 2012.
  26. Improving Performance of Nested Loops on Reconfigurable Array Processors, Yongjoo Kim, Jongeun Lee*, Toan X. Mai and Yunheung Paek, ACM Transactions on Architecture and Code Optimization (TACO), 8(4), pp. 32:1-32:23, ACM, January, 2012.
  27. High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures, Yongjoo Kim, Jongeun Lee*, Aviral Shrivastava, Jonghee W. Yoon, Doosan Cho and Yunheung Paek, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 30(11), pp. 1599-1609, IEEE, November, 2011.
  28. Memory Access Optimization in Compilation for Coarse Grained Reconfigurable Architectures, Yongjoo Kim, Jongeun Lee*, Aviral Shrivastava and Yunheung Paek, ACM Transactions on Design Automation of Electronic Systems (TODAES), 16(4), pp. 42:1-42:27, ACM, October, 2011.
  29. Fast graph-based instruction selection for multi-output instructions, Jonghee M. Youn, Jongwon Lee, Yunheung Paek, Jongeun Lee*, Hanno Scharwaechter and Rainer Leupers, Software: Practice & Experience (SP&E), 41(6), pp. 717-736, Wiley, May, 2011.
  30. Static Analysis of Register File Vulnerability, Jongeun Lee and Aviral Shrivastava, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 30(4), pp. 607-616, IEEE, April, 2011.
  31. Binary Acceleration Using Coarse-Grained Reconfigurable Architecture, Jong Kyung Paek, Kiyoung Choi and Jongeun Lee, SIGARCH Computer Architecture News, 38(4), pp. 33-39, ACM, September, 2010.
  32. A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files, Jongeun Lee and Aviral Shrivastava, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 29(7), pp. 1018-1027, IEEE Press, July, 2010.
  33. Operation and Data Mapping for CGRAs with Multi-Bank Memory, Yongjoo Kim, Jongeun Lee*, Aviral Shrivastava and Yunheung Paek, ACM SIGPLAN Notices (LCTES '10), 45(4), pp. 17-26, April, 2010. (18 papers accepted out of 58 submissions, 31.0% acceptance rate)
  34. Cache Vulnerability Equations for Protecting Data in Embedded Processor Caches from Soft Errors, Aviral Shrivastava, Jongeun Lee* and Reiley Jeyapaul, ACM SIGPLAN Notices (LCTES '10), 45(4), pp. 143-152, April, 2010. (Second Highest Ranked Paper)
  35. A Software-Only Solution to Use Scratch Pads for Stack Data, Aviral Shrivastava, Arun Kannan and Jongeun Lee*, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 28(11), pp. 1719-1727, November, 2009.
  36. A Compiler Optimization to Reduce Soft Errors in Register Files, Jongeun Lee and Aviral Shrivastava, ACM SIGPLAN Notices (LCTES '09), 44(7), pp. 41-49, ACM, July, 2009. (18 papers accepted out of 81 submissions, 22.2% acceptance rate)
  37. Evaluating Memory Architectures for Media Applications on Coarse-grained Reconfigurable Architectures, Jongeun Lee, Kiyoung Choi and Nikil Dutt, International Journal of Embedded Systems, 3(3), pp. 119-127, Inderscience, July, 2008.
  38. Instruction Set Synthesis with Efficient Instruction Encoding for Configurable Processors, Jongeun Lee, Kiyoung Choi and Nikil Dutt, ACM Transactions on Design Automation of Electronic Systems (TODAES), 12(1), pp. 1-37, ACM, January, 2007.
  39. System Level Architecture Evaluation and Optimization: an Industrial Case Study with AMBA3 AXI, Jongeun Lee, Woo-Cheol Kwon, Taehoon Kim, Eui-Young Chung, Kyu-Myoung Choi, Jeong-Taek Kong, Soo-Kwan Eo and David Gwilt, Journal of Semiconductor Technology and Science, 5(4), pp. 229-237, , 2005.
  40. An Algorithm for Mapping Loops onto Coarse-Grained Reconfigurable Architectures, Jongeun Lee, Kiyoung Choi and Nikil D. Dutt, ACM SIGPLAN Notices (LCTES '03), 38(7), pp. 183-188, July, 2003.
  41. Compilation Approach for Coarse-grained Reconfigurable Architectures, Jongeun Lee, Kiyoung Choi and Nikil Dutt, IEEE Design & Test, 20(1), pp. 26-33, January/February, 2003.

Domestic Journal Articles


  1. Speech Independent Speaker Recognition System Using Local Accumulation Based Decision Network, Jongeun Lee and Jinyoung Choi, Korean Fuzzy Logic & Intelligent System Society, 8(2), pp. 82-95, , 1998.

Domestic Conference Papers


  1. FPGA Prototyping of Local Binary Convolutional Neural Network, Segi Lee, Aidyn Zhakatayev and Jongeun Lee**, Proc. of the 26th Korean Conference on Semiconductors, February, 2019.
  2. Reducing FPGA Area Using Nano-Switch Devices in Inter and Intra-Logic Routing, Aidyn Zhakatayev and Jongeun Lee**, Proc. of the 25th Korean Conference on Semiconductors, February, 2018.
  3. Pipelining Nested Loops with Triangular Iteration Space for High-Level Synthesis, Atul Rahman, Hyeonuk Sim and Jongeun Lee**, Proc. of the 22nd Korean Conference on Semiconductors, February, 2015.
  4. Optimization of Streaming Application with Limited Scratch-pad Memory on Coarse-Grained Reconfigurable Architecture, Hongsik Lee and Jongeun Lee, Proc. of the 22nd Korean Conference on Semiconductors, February, 2015.
  5. Optimal Resource-aware Mapping of Stream Graphs to GP-GPUs, Dong Nguyen and Jongeun Lee, Proc. of the 22nd Korean Conference on Semiconductors, February, 2015.
  6. New Processing Element for Imperfect Nested Loops on Coarse Grained Reconfigurable Architecture, Seongseok Seo, Hyeonuk Sim and Jongeun Lee, Proc. of the 21st Korean Conference on Semiconductors, February, 2014.
  7. FPGA Prototyping of Programmable Regular Iterator Generator, Hyeonuk Sim, Seongseok Seo and Jongeun Lee, Proc. of the 21st Korean Conference on Semiconductors, February, 2014.
  8. Mapping DSP Loops to Reconfigurable Processor Accelerators, Sungsok Seo, Yeonghun Jeong and Jongeun Lee, Proc. of the 20th Korean Conference on Semiconductors, February, 2013.
  9. Selective Execution of Conditional Statements for CGRAs, Yeonghun Jeong, Sungsok Seo and Jongeun Lee, Proc. of the 20th Korean Conference on Semiconductors, February, 2013. (Best Paper Award)
  10. Promoting Data Reuse on Shared Memory of Hybrid System, Toan X. Mai, Yeonghun Jeong and Jongeun Lee, Proc. of the 19th Korean Conference on Semiconductors, pp. 593-594, February, 2012.
  11. Design Space Exploration of Reconfigurable ALU Array (RAA) Architectures, Jongeun Lee, Kiyoung Choi and Nikil Dutt, Proc. of SoC Design Conference, , 2003.

Master's Theses


  1. Aidyn Zhakatayev, Sign-Magnitude Stochastic Computing, Ulsan National Institute of Science and Technology, August, 2018.
    Thesis Committee: Jongeun Lee (Chair), Woongki Baek, and Seokhyeong Kang.
  2. Daewoo Kim, Reconfigurable SIMD Multiply-and-Accumulator and Efficient On-Chip Training of Deep Neural Networks, Ulsan National Institute of Science and Technology, August, 2018.
    Thesis Committee: Jongeun Lee (Chair), Woongki Baek, and Seokhyeong Kang.
  3. Atul Rahman, Efficient FPGA Acceleration of Convolutional Deep Neural Networks, Ulsan National Institute of Science and Technology, August, 2016.
    Thesis Committee: Jongeun Lee (Chair), Woongki Baek, and Seokhyeong Kang.
  4. Dong Nguyen, Communication-aware Mapping of Stream Graphs for Multi-GPU Platforms, Ulsan National Institute of Science and Technology, February, 2016.
    Thesis Committee: Jongeun Lee (Chair), Woongki Baek, and Wonki Jeong.
  5. Hongsik Lee, Application-Level Performance Improvement for Stream Program on CGRA-based systems, Ulsan National Institute of Science and Technology, February, 2016.
    Thesis Committee: Jongeun Lee (Chair), Woongki Baek, and Seokhyeong Kang.
  6. Seongseok Seo, Scaling Kernel Speedup to Application-level Performance with CGRAs: Stream Program Approach, Ulsan National Institute of Science and Technology, February, 2014.
    Thesis Committee: Jongeun Lee (Chair), Won-ki Jeong, and Giljin Jang.
  7. Yeonghun Jeong, Evaluator-executor Transformation for Efficient Conditional Statements on CGRA, Ulsan National Institute of Science and Technology, June, 2013.
    Thesis Committee: Jongeun Lee (Chair), Won-ki Jeong, and Youngri Choi.
  8. Toan X. Mai, Runtime and Install-time Binary Translation for Reconfigurable Accelerators, Ulsan National Institute of Science and Technology, February, 2013.
    Thesis Committee: Jongeun Lee (Chair), Beomseok Nam, and Won-Ki Jeong.